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| MCP6071/2/4 110 A, High Precision Op Amps Features * * * * * * * * Low Offset Voltage: 150 V (maximum) Low Quiescent Current: 110 A (typical) Rail-to-Rail Input and Output Wide Supply Voltage Range: 1.8V to 6.0V Gain Bandwidth Product: 1.2 MHz (typical) Unity Gain Stable Extended Temperature Range: -40C to +125C No Phase Reversal Description The Microchip Technology Inc. MCP6071/2/4 family of operational amplifiers (op amps) has low input offset voltage (150 V, maximum) and rail-to-rail input and output operation. This family is unity gain stable and has a gain bandwidth product of 1.2 MHz (typical). These devices operate with a single supply voltage as low as 1.8V, while drawing low quiescent current per amplifier (110 A, typical). These features make the family of op amps well suited for single-supply, high precision, battery-powered applications. The MCP6071/2/4 family is offered in single (MCP6071), dual (MCP6072), and quad (MCP6074) configurations. The MCP6071/2/4 is designed with Microchip's advanced CMOS process. All devices are available in the extended temperature range, with a power supply range of 1.8V to 6.0V. Applications * * * * * * * Automotive Portable Instrumentation Sensor Conditioning Battery Powered Systems Medical Instrumentation Test Equipment Analog Filters Package Types MCP6071 SOIC NC 1 VIN- 2 VIN+ 3 VSS 4 8 NC 7 VDD 6 VOUT 5 NC Design Aids * * * * * SPICE Macro Models FilterLab(R) Software MAPS (Microchip Advanced Part Selector) Analog Demonstration and Evaluation Boards Application Notes MCP6072 SOIC VOUTA 1 VINA- 2 VINA+ 3 VSS 4 8 VDD 7 VOUTB 6 VINB- 5 VINB+ Typical Application RL ZIN MCP6071 C Z IN = RL + jL L = R L RC R Gyrator VOUT MCP6071 2x3 TDFN NC 1 VIN- 2 VIN+ 3 VSS 4 EP 9 8 NC 7 VDD 5 NC VOUTA 1 VINA- 2 VSS 4 MCP6072 2x3 TDFN 8 VDD EP 9 7 VOUTB 6 VINB- 5 VINB+ 6 VOUT VINA+ 3 MCP6071 SOT-23-5 VOUT 1 VSS 2 VIN+ 3 5 VDD 4 VIN- MCP6074 SOIC, TSSOP VOUTA 1 VINA- 2 VINA+ 3 VDD 4 VINB+ 5 VINB- 6 VOUTB 7 14 VOUTD 13 VIND- 12 VIND+ 11 VSS 10 VINC+ 9 VINC- 8 VOUTC * Includes Exposed Thermal Pad (EP); see Table 3-1. (c) 2010 Microchip Technology Inc. DS22142B-page 1 MCP6071/2/4 NOTES: DS22142B-page 2 (c) 2010 Microchip Technology Inc. MCP6071/2/4 1.0 1.1 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. See 4.1.2 "Input Voltage Limits" VDD - VSS ........................................................................7.0V Current at Input Pins .....................................................2 mA Analog Inputs (VIN+, VIN-) .......... VSS - 1.0V to VDD + 1.0V All Other Inputs and Outputs ......... VSS - 0.3V to VDD + 0.3V Difference Input Voltage ...................................... |VDD - VSS| Output Short-Circuit Current .................................continuous Current at Output and Supply Pins ............................30 mA Storage Temperature ....................................-65C to +150C Maximum Junction Temperature (TJ) .......................... +150C ESD protection on all pins (HBM; MM) ................ 4 kV; 400V 1.2 Specifications DC ELECTRICAL SPECIFICATIONS TABLE 1-1: Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +6.0V, VSS= GND, TA= +25C, VCM = VDD/2, VOUT VDD/2, VL = VDD/2 and RL = 10 k to VL. (Refer to Figure 1-1). Parameters Input Offset Input Offset Voltage Input Offset Drift with Temperature VOS VOS/TA VOS/TA Power Supply Rejection Ratio Input Bias Current and Impedance Input Bias Current IB IB IB Input Offset Current Common Mode Input Impedance Differential Input Impedance Common Mode Common Mode Input Voltage Range Common Mode Rejection Ratio VCMR VCMR CMRR VSS-0.15 VSS-0.3 72 74 72 74 Note 1: -- -- 89 91 87 89 VDD+0.15 VDD+0.3 -- -- -- -- V V dB dB dB dB VDD = 1.8V (Note 1) VDD = 6.0V (Note 1) VCM = -0.15V to 1.95V, VDD = 1.8V VCM = -0.3V to 6.3V, VDD = 6.0V VCM = 3.0V to 6.3V, VDD = 6.0V VCM = -0.3V to 3.0V, VDD = 6.0V IOS ZCM ZDIFF -- -- -- -- -- -- 1.0 60 1100 1.0 10 ||6 1013||6 13 Sym Min -150 -- -- 70 Typ -- 1.5 4.0 87 Max +150 -- -- -- 100 -- 5000 -- -- -- Units V Conditions VDD = 3.0V, VCM = VDD/3 V/C TA= -40C to +85C, VDD = 3.0V, VCM = VDD/3 V/C TA= +85C to +125C, VDD = 3.0V, VCM = VDD/3 dB pA pA pA pA ||pF ||pF TA = +85C TA = +125C VCM = VSS PSRR Figure 2-13 shows how VCMR changed across temperature. (c) 2010 Microchip Technology Inc. DS22142B-page 3 MCP6071/2/4 TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +6.0V, VSS= GND, TA= +25C, VCM = VDD/2, VOUT VDD/2, VL = VDD/2 and RL = 10 k to VL. (Refer to Figure 1-1). Parameters Open-Loop Gain DC Open-Loop Gain (Large Signal) Output Maximum Output Voltage Swing Output Short-Circuit Current Power Supply Supply Voltage Quiescent Current per Amplifier Note 1: VDD IQ 1.8 50 -- 110 6.0 170 V A IO = 0, VDD = 6.0V VCM = 0.9VDD VOL, VOH ISC VSS+15 -- -- -- 7 28 VDD-15 -- -- mV mA mA 0.5V input overdrive VDD = 1.8V VDD = 6.0V AOL 95 115 -- dB 0.2V < VOUT <(VDD-0.2V) VCM = VSS Sym Min Typ Max Units Conditions Figure 2-13 shows how VCMR changed across temperature. TABLE 1-2: AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +1.8 to +6.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 10 k to VL and CL = 60 pF. (Refer to Figure 1-1). Parameters AC Response Gain Bandwidth Product Phase Margin Slew Rate Noise Input Noise Voltage Input Noise Voltage Density Input Noise Current Density Eni eni ini -- -- -- 4.3 19 0.6 -- -- -- Vp-p nV/Hz fA/Hz f = 0.1 Hz to 10 Hz f = 10 kHz f = 1 kHz GBWP PM SR -- -- -- 1.2 57 0.5 -- -- -- MHz V/s G = +1 V/V Sym Min Typ Max Units Conditions TABLE 1-3: TEMPERATURE SPECIFICATIONS Parameters Sym TA TA JA JA JA JA JA Min -40 -65 -- -- -- -- -- Typ -- -- 220.7 52.5 149.5 95.3 100 Max +125 +150 -- -- -- -- -- Units C C C/W C/W C/W C/W C/W Conditions Note 1 Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +6.0V and VSS = GND. Temperature Ranges Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 5L-SOT-23 Thermal Resistance, 8L-2x3 TDFN Thermal Resistance, 8L-SOIC Thermal Resistance, 14L-SOIC Thermal Resistance, 14L-TSSOP Note 1: The internal junction temperature (TJ) must not exceed the absolute maximum specification of +150C. DS22142B-page 4 (c) 2010 Microchip Technology Inc. MCP6071/2/4 1.3 Test Circuits CF 6.8 pF RG 100 k VP VIN+ MCP607X VIN- VM RG 100 k RF 100 k CF 6.8 pF RL 10 k VOUT CL 60 pF CB1 100 nF RF 100 k VDD VDD/2 The circuit used for most DC and AC tests is shown in Figure 1-1. This circuit can independently set VCM and VOUT; see Equation 1-1. Note that VCM is not the circuit's common mode voltage ((VP + VM)/2), and that VOST includes VOS plus the effects (on the input offset error, VOST) of temperature, CMRR, PSRR and AOL. EQUATION 1-1: G DM = R F R G V CM = ( VP + VDD 2 ) 2 V OST = V IN- - V IN+ V OUT = ( V DD 2 ) + ( V P - V M ) + V OST ( 1 + G DM ) Where: GDM = Differential Mode Gain VCM = Op Amp's Common Mode Input Voltage VOST = Op Amp's Total Input Offset Voltage (V/V) (V) (mV) CB2 1 F VL FIGURE 1-1: AC and DC Test Circuit for Most Specifications. (c) 2010 Microchip Technology Inc. DS22142B-page 5 MCP6071/2/4 NOTES: DS22142B-page 6 (c) 2010 Microchip Technology Inc. MCP6071/2/4 2.0 Note: TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 10 k to VL and CL = 60 pF. 14% 12% 10% 8% 6% 4% 2% 0% -120 -90 -60 30 60 90 120 -150 150 -30 0 Input Offset Voltage (V) Input Offset Voltage (V) 1244 Samples VDD = 3.0V VCM = VDD /3 1000 800 600 400 200 0 -200 -400 -600 -800 -1000 -0.5 Percentage of Occurences VDD = 6.0V Representative Part TA = -40C TA = +25C TA = +85C TA = +125C 2.0 3.0 4.0 5.0 6.0 2.1 0.0 0.5 1.0 1.5 2.5 3.5 4.5 5.5 1.9 Common Mode Input Voltage (V) FIGURE 2-1: VDD = 3.0V. 27% Input Offset Voltage with FIGURE 2-4: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 6.0V. 1000 800 600 400 200 0 -200 -400 -600 -800 -1000 -0.5 Percentage of Occurences Input Offset Voltage (V) 24% 21% 18% 15% 12% 9% 6% 3% 0% 1244 Samples VDD = 3.0V VCM = VDD/3 TA = -40C to +85C VDD = 3.0V Representative Part TA = -40C TA = +25C TA = +85C TA = +125C 0.4 0.7 -0.2 2.8 0.1 2.2 2.5 1.0 1.3 1.6 1.9 3.1 -20 -16 -12 12 16 Input Offset Drift with Temperature (V/C) 20 Common Mode Input Voltage (V) FIGURE 2-2: Input Offset Voltage Drift with VDD = 3.0V and TA +85C. 27% 24% 21% 18% 15% 12% 9% 6% 3% 0% -20 -16 -8 -12 -4 16 0 4 8 12 20 Input Offset Drift with Temperature (V/C) FIGURE 2-5: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 3.0V. 1000 800 600 400 200 0 -200 -400 -600 -800 -1000 -0.5 Percentage of Occurences Input Offset Voltage (V) 1244 Samples VDD = 3.0V VCM = VDD/3 TA = +85C to +125C VDD = 1.8V Representative Part TA = -40C TA = +25C TA = +85C TA = +125C -0.3 -0.1 0.1 0.7 0.3 0.5 0.9 1.1 1.3 1.5 1.7 Common Mode Input Voltage (V) FIGURE 2-3: Input Offset Voltage Drift with VDD = 3.0V and TA +85C. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 1.8V. (c) 2010 Microchip Technology Inc. DS22142B-page 7 2.3 3.4 -8 -4 0 4 8 6.5 MCP6071/2/4 Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 10 k to VL and CL = 60 pF. 350 250 150 50 -50 -150 -250 -350 0.5 1.5 2.5 3.5 4.5 5.5 0.0 1.0 2.0 3.0 4.0 5.0 6.0 Output Voltage (V) VDD = 1.8V VDD = 3.0V VDD = 6.0V Representative Part Input Noise Voltage Density (nV/Hz) Input Offset Voltage (V) 40 35 30 25 20 15 10 5 0 1.0 2.5 4.0 -0.5 5.5 0.0 0.5 1.5 2.0 3.0 3.5 4.5 5.0 6.0 Common Mode Input Voltage (V) 6.5 f = 10 kHz VDD = 6.0V FIGURE 2-7: Output Voltage. 1000 800 600 400 200 0 -200 -400 -600 -800 -1000 1.5 Input Offset Voltage vs. FIGURE 2-10: Input Noise Voltage Density vs. Common Mode Input Voltage. 110 CMRR, PSRR (dB) Input Offset Voltage (V) TA = -40C TA = +25C TA = +85C TA = +125C Representative Part 100 90 80 70 60 50 40 30 20 10 10 PSRR+ PSRR- Representative Part CMRR 2.0 4.0 5.0 6.0 2.5 3.0 3.5 4.5 5.5 6.5 Power Supply Voltage (V) 100 100 1k 10k 1000 10000 Frequency (Hz) 100k 100000 1M 1000000 FIGURE 2-8: Input Offset Voltage vs. Power Supply Voltage. 1,000 FIGURE 2-11: Frequency. 110 105 100 95 90 85 80 75 70 65 60 -50 CMRR, PSRR vs. Input Noise Voltage Density (nV/Hz) CMRR (VDD = 6.0V, VCM = -0.3V to 6.3V) 100 PSRR, CMRR (dB) PSRR (VDD = 1.8V to 6.0V, VCM = VSS ) 10 0.1 1.E-1 1 1.E+0 10 1.E+1 100 1.E+2 1k 1.E+3 10k 1.E+4100k 1.E+5 Frequency (Hz) -25 0 25 50 75 Ambient Temperature (C) 100 125 FIGURE 2-9: vs. Frequency. Input Noise Voltage Density FIGURE 2-12: Temperature. CMRR, PSRR vs. Ambient DS22142B-page 8 (c) 2010 Microchip Technology Inc. MCP6071/2/4 Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 10 k to VL and CL = 60 pF. 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 -0.05 -0.10 -0.15 -0.20 -0.25 -0.30 -0.35 150 140 Quiescent Current (A/Amplifier) 130 120 110 100 90 80 70 60 VDD = 1.8V VCM = 0.9VDD VCMR_H - VDD @ VDD = 6.0V @ VDD = 3.0V @ VDD = 1.8V VCMR_L - VSS @ VDD = 1.8V VOL - VSS @ VDD = 3.0V VOL - VSS @ VDD = 6.0V VDD = 6.0V VCM = 0.9VDD Common Mode Input Voltage Range Limit (V) -50 -25 0 25 50 75 100 Ambient Temperature (C) 125 -50 -25 0 25 50 75 100 Ambient Temperature (C) 125 FIGURE 2-13: Common Mode Input Voltage Range Limit vs. Ambient Temperature. 10000 Input Bias and Offset Currents (pA) 1000 100 10 Input Offset Current Input Bias Current FIGURE 2-16: Quiescent Current vs Ambient Temperature with VCM = 0.9VDD. 180 160 140 120 100 80 60 40 20 0 0.0 0.5 4.0 4.5 1.0 1.5 2.0 2.5 3.0 3.5 TA = +125C TA = +85C TA = +25C TA = -40C 5.0 5.5 6.0 6.5 25 45 65 85 105 Ambient Temperature (C) 125 Power Supply Voltage (V) FIGURE 2-14: Input Bias, Offset Currents vs. Ambient Temperature. 10000 Input Bias Current (pA) VDD = 6.0V FIGURE 2-17: Quiescent Current vs. Power Supply Voltage with VCM = 0.9VDD. 120 Open-Loop Gain (dB) 100 80 60 40 20 0 -20 Frequency (Hz) Frequency (Hz) VDD = 6.0V Open-Loop Gain 0 Open-Loop Phase () -30 -60 -90 -120 -150 -180 -210 1000 TA = +125C Open-Loop Phase 100 10 1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Common Mode Input Votlage (V) TA = +85C 1.E-01 1.E+00 1.E+01 100 1.E+03 10k 100k 1.E+06 1.E+07 0.1 1 10 1.E+02 1k 1.E+04 1.E+05 1M 10M FIGURE 2-15: Input Bias Current vs. Common Mode Input Voltage. FIGURE 2-18: Frequency. Open-Loop Gain, Phase vs. (c) 2010 Microchip Technology Inc. DS22142B-page 9 7.0 1 Quiescent Current (A/Amplifier) VDD = 6.0V VCM = VDD VDD = 6.0V VCM = 0.9VDD MCP6071/2/4 Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 10 k to VL and CL = 60 pF. 150 145 140 135 130 125 120 115 110 105 100 DC-Open-Loop Gain (dB) Gain Bandwidth Product (MHz) 1.0 0.8 0.6 0.4 0.2 0.0 VDD = 6.0V 100 80 60 40 20 0 Phase Margin RL = 10 k VSS + 0.2V < VOUT < VDD - 0.2V 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Power Supply Voltage (V) 5.5 6.0 FIGURE 2-19: DC Open-Loop Gain vs. Power Supply Voltage. 150 145 140 135 130 125 120 115 110 105 100 0.00 FIGURE 2-22: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage. 1.8 Gain Bandwidth Product (MHz) 180 Gain Bandwidth Product DC-Open-Loop Gain (dB) VDD = 6.0V 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -50 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Common Mode Input Voltage (V) 160 120 100 80 60 40 20 0 125 Phase Margin () Phase Margin () 140 VDD = 1.8V Large Signal AOL VDD = 6.0V Phase Margin 0.05 0.10 0.15 0.20 0.25 Output Voltage Headroom V DD - VOH or VOL - VSS (V) -25 0 25 50 75 100 Ambient Temperature (C) FIGURE 2-20: DC Open-Loop Gain vs. Output Voltage Headroom. 150 Channel to Channel Separation (dB) 140 130 120 110 100 90 Input Referred FIGURE 2-23: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. 1.8 Gain Bandwidth Product (MHz) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -50 -25 0 25 50 75 100 Ambient Temperature (C) VDD = 1.8V Phase Margin Gain Bandwidth Product 180 160 140 120 100 80 60 40 20 0 125 80 100 1k 10k 100k 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1M 1.00E+06 Frequency (Hz) FIGURE 2-21: Channel-to-Channel Separation vs. Frequency ( MCP6072/4 only). FIGURE 2-24: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. DS22142B-page 10 (c) 2010 Microchip Technology Inc. Phase Margin () 1.8 1.6 1.4 1.2 Gain Bandwidth Product 180 160 140 120 MCP6071/2/4 Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 10 k to VL and CL = 60 pF. Output Short Circuit Current (mA) 40 35 30 25 20 15 10 5 0 0.5 2.0 4.0 5.5 0.0 1.0 1.5 2.5 3.0 3.5 4.5 5.0 6.0 Power Supply Voltage (V) 16.0 Output Voltage Headroom VDD - VOH or VOL - VSS (mV) TA = -40C TA = +25C TA = +85C TA = +125C 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 -50 -25 0 25 50 75 100 Ambient Temperature (C) 125 VOL - VSS VDD - VOH FIGURE 2-25: Ouput Short Circuit Current vs. Power Supply Voltage. 10 FIGURE 2-28: Output Voltage Headroom vs. Ambient Temperature. 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -50 Output Voltage Swing (V P-P) VDD = 6.0V VDD = 1.8V Falling Edge, VDD = 6.0V Falling Edge, VDD = 1.8V 1 Slew Rate (V/s) Rising Edge, VDD = 6.0V Rising Edge, VDD = 1.8V 0.1 1k 1000 10k 10000 100k 100000 1M 1000000 Frequency (Hz) -25 0 25 50 75 Ambient Temperature (C) 100 125 FIGURE 2-26: Frequency. 60 55 50 45 40 35 30 25 20 15 10 5 0 Output Voltage Swing vs. FIGURE 2-29: Temperature. Slew Rate vs. Ambient Ratio of Output Headroom to Current (mV/mA) (VOL - VSS )/(-IOUT) (VDD - VOH )/IOUT (VOL - VSS )/(-IOUT) VDD = 6.0V Output Voltage (50 mV/div) (VDD - VOH)/IOUT VDD = 1.8V VDD = 6.0V G = +1 V/V 0.1 1 Output Current (mA) 10 Time (2 s/div) FIGURE 2-27: Ratio of Output Voltage Headroom to Output Current vs. Output Current. FIGURE 2-30: Pulse Response. Small Signal Non-Inverting (c) 2010 Microchip Technology Inc. DS22142B-page 11 MCP6071/2/4 Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 10 k to VL and CL = 60 pF. 7.0 Output Voltage (50 mV/div) VDD = 6.0V G = -1 V/V 6.0 Output Voltage (V) 5.0 4.0 3.0 2.0 1.0 0.0 VDD = 6.0V G = +2 V/V VIN VOUT Time (2 s/div) -1.0 Time (0.1 ms/div) FIGURE 2-31: Response. 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Small Signal Inverting Pulse FIGURE 2-34: The MCP6071/2/4 Shows No Phase Reversal. 1000 Closed Loop Output Impedance () Output Voltage (V) 100 10 VDD = 6.0V G = +1 V/V GN: 101 V/V 11 V/V 1 V/V 10 10 1 Time (0.02 ms/div) 100 100 1000 1k 10000 10k Frequency (Hz) 100000 100k 1000000 1M FIGURE 2-32: Pulse Response. 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Large Signal Non-Inverting FIGURE 2-35: Closed Loop Output Impedance vs. Frequency. 1.E-03 1m 1.E-04 100 Output Voltage (V) VDD = 6.0V G = -1 V/V 1.E-05 10 1.E-06 1 -IIN (A) 1.E-07 100n 1.E-08 10n 1.E-09 1n 1.E-10 100p 1.E-11 10p 1.E-12 1p TA = -40C TA = +25C TA = +85C TA = +125C Time (0.02 ms/div) -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 VIN (V) FIGURE 2-33: Response. Large Signal Inverting Pulse FIGURE 2-36: Measured Input Current vs. Input Voltage (below VSS). DS22142B-page 12 (c) 2010 Microchip Technology Inc. MCP6071/2/4 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE MCP6072 SOIC 1 2 3 8 5 6 7 -- -- -- 4 -- -- -- -- -- 2x3 TDFN 1 2 3 8 5 6 7 -- -- -- 4 -- -- -- -- 9 MCP6074 SOIC, TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 -- -- Symbol VOUT, VOUTA VIN-, VINA- VIN+, VINA+ VDD VINB+ VINB- VOUTB VOUTC VINC- VINC+ VSS VIND+ VIND- VOUTD NC EP Description Analog Output (op amp A) Inverting Input (op amp A) Non-inverting Input (op amp A) Positive Power Supply Non-inverting Input (op amp B) Inverting Input (op amp B) Analog Output (op amp B) Analog Output (op amp C) Inverting Input (op amp C) Non-inverting Input (op amp C) Negative Power Supply Non-inverting Input (op amp D) Inverting Input (op amp D) Analog Output (op amp D) No Internal Connection Exposed Thermal Pad (EP); must be connected to VSS. MCP6071 SOIC 6 2 3 7 -- -- -- -- -- -- 4 -- -- -- 1, 5, 8 -- SOT-23-5 2x3 TDFN 1 4 3 5 -- -- -- -- -- -- 2 -- -- -- -- -- 6 2 3 7 -- -- -- -- -- -- 4 -- -- -- 1, 5, 8 9 3.1 Analog Outputs 3.3 Power Supply Pins The output pins are low-impedance voltage sources. 3.2 Analog Inputs The non-inverting and inverting inputs are highimpedance CMOS inputs with low bias currents. The positive power supply (VDD) is 1.8V to 6.0V higher than the negative power supply (VSS). For normal operation, the other pins are at voltages between VSS and VDD. Typically, these parts are used in a single (positive) supply configuration. In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need bypass capacitors. 3.4 Exposed Thermal Pad (EP) There is an internal electrical connection between the Exposed Thermal Pad (EP) and the VSS pin; they must be connected to the same potential on the Printed Circuit Board (PCB). (c) 2010 Microchip Technology Inc. DS22142B-page 13 MCP6071/2/4 NOTES: DS22142B-page 14 (c) 2010 Microchip Technology Inc. MCP6071/2/4 4.0 APPLICATION INFORMATION D1 V1 MCP607X V2 VOUT D2 VDD U1 The MCP6071/2/4 family of op amps is manufactured using Microchip's state-of-the-art CMOS process and is specifically designed for low-power, high precision applications. 4.1 4.1.1 Rail-to-Rail Input PHASE REVERSAL FIGURE 4-2: Inputs. The MCP6071/2/4 op amps are designed to prevent phase reversal when the input pins exceed the supply voltages. Figure 2-34 shows the input voltage exceeding the supply voltage without any phase reversal. Protecting the Analog A significant amount of current can flow out of the inputs when the Common Mode voltage (VCM) is below ground (VSS). See Figure 2-36. 4.1.2 INPUT VOLTAGE LIMITS 4.1.3 INPUT CURRENT LIMITS In order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the voltages at the input pins (see Section 1.1, Absolute Maximum Ratings ). The ESD protection on the inputs can be depicted as shown in Figure 4-1. This structure was chosen to protect the input transistors and to minimize input bias current (IB). VDD Bond Pad In order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the voltages at the input pins (see Section 1.1, Absolute Maximum Ratings ). Figure 4-3 shows one approach to protecting these inputs. The resistors R1 and R2 limit the possible currents in or out of the input pins (and the ESD diodes, D1 and D2). The diode currents will go through either VDD or VSS. VDD D1 V1 R1 V2 R2 MCP607X D2 U1 VOUT VIN+ Bond Pad Input Stage Bond V - IN Pad Bond VSS Pad min(R1,R2) > FIGURE 4-1: Structures. Simplified Analog Input ESD VSS - min (V1,V2) 2 mA max(V1,V2) - VDD min(R1,R2) > 2 mA The input ESD diodes clamp the inputs when they try to go more than one diode drop below VSS. They also clamp any voltages that go well above VDD; their breakdown voltage is high enough to allow normal operation, but not low enough to protect against slow over-voltage (beyond VDD) events. Very fast ESD events (that meet the spec) are limited so that damage does not occur. In some applications, it may be necessary to prevent excessive voltages from reaching the op amp inputs. Figure 4-2 shows one approach to protecting these inputs. FIGURE 4-3: Inputs. 4.1.4 Protecting the Analog NORMAL OPERATION The input stage of the MCP6071/2/4 op amps use two differential input stages in parallel. One operates at a low common mode input voltage (VCM), while the other operates at a high VCM. With this topology, the device operates with a VCM up to 300 mV above VDD and 300 mV below VSS. (See Figure 2-13). The input offset voltage is measured at VCM = VSS - 0.3V and VDD + 0.3V to ensure proper operation. The transition between the input stages occurs when VCM is near VDD - 1.1V (See Figures 2-4, 2-5 and Figure 2-6). For the best distortion performance and gain linearity, with non-inverting gains, avoid this region of operation. (c) 2010 Microchip Technology Inc. DS22142B-page 15 MCP6071/2/4 4.2 Rail-to-Rail Output The output voltage range of the MCP6071/2/4 op amps is VSS + 15 mV (minimum) and VDD - 15 mV (maximum) when RL = 10 k is connected to VDD/2 and VDD = 6.0V. Refer to Figures 2-27 and 2-28 for more information. After selecting RISO for your circuit, double-check the resulting frequency response peaking and step response overshoot. Modify RISO's value until the response is reasonable. Bench evaluation and simulations with the MCP6071/2/4 SPICE macro model are very helpful. 4.3 Capacitive Loads 4.4 Supply Bypass Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop's phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. While a unity-gain buffer (G = +1) is the most sensitive to capacitive loads, all gains show the same general behavior. When driving large capacitive loads with these op amps (e.g., > 100 pF when G = +1), a small series resistor at the output (RISO in Figure 4-4) improves the feedback loop's phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitance load. With this family of operational amplifiers, the power supply pin (VDD for single-supply) should have a local bypass capacitor (i.e., 0.01 F to 0.1 F) within 2 mm for good high frequency performance. It can use a bulk capacitor (i.e., 1 F or larger) within 100 mm to provide large, slow currents. This bulk capacitor can be shared with other analog parts. 4.5 Unused Op Amps An unused op amp in a quad package (MCP6074) should be configured as shown in Figure 4-6. These circuits prevent the output from toggling and causing crosstalk. Circuit A sets the op amp at its minimum noise gain. The resistor divider produces any desired reference voltage within the output voltage range of the op amp; the op amp buffers that reference voltage. Circuit B uses the minimum number of components and operates as a comparator, but it may draw more current. 1/4 MCP6074 (A) VDD R1 R2 VDD VREF 1/4 MCP6074 (B) VDD - VIN MCP607X + RISO VOUT CL FIGURE 4-4: Output Resistor, RISO Stabilizes Large Capacitive Loads. Figure 4-5 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit's noise gain. For non-inverting gains, GN and the Signal Gain are equal. For inverting gains, GN is 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V). 1000 VDD = 6.0 V RL = 10 k R2 VREF = VDD x -------------------R1 + R2 FIGURE 4-6: Unused Op Amps. ISO () Recommended R 100 GN: 1 V/V 2 V/V 5 V/V 10 1 10p 100p 1n 10n 0.1 1 1.E-11 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06 Normalized Load Capacitance; CL/GN (F) FIGURE 4-5: Recommended RISO Values for Capacitive Loads. DS22142B-page 16 (c) 2010 Microchip Technology Inc. MCP6071/2/4 4.6 PCB Surface Leakage In applications where low input bias current is critical, Printed Circuit Board (PCB) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012. A 5V difference would cause 5 pA of current to flow; which is greater than the MCP6071/2/4 family's bias current at +25C (1.0 pA, typical). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 4-7. Guard Ring VIN- VIN+ VSS FIGURE 4-7: for Inverting Gain. 1. Example Guard Ring Layout 2. Non-inverting Gain and Unity-Gain Buffer: a.Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b.Connect the guard ring to the inverting input pin (VIN-). This biases the guard ring to the common mode input voltage. Inverting Gain and Transimpedance Gain Amplifiers (convert current to voltage, such as photo detectors): a.Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). b.Connect the inverting pin (VIN-) to the input with a wire that does not touch the PCB surface. (c) 2010 Microchip Technology Inc. DS22142B-page 17 MCP6071/2/4 4.7 4.7.1 Application Circuits GYRATOR 4.7.2 INSTRUMENTATION AMPLIFIER The MCP6071/2/4 op amps can be used in gyrator applications. The gyrator is an electric circuit which can make a capacitive circuit behave inductively. Figure 4-8 shows an example of a gyrator simulating inductance, with an approximately equivalent circuit below. The two ZIN have similar values in typical applications. The primary application for a gyrator is to reduce the size and cost of a system by removing the need for bulky, heavy and expensive inductors. For example, RLC bandpass filter characteristics can be realized with capacitors, resistors and operational amplifiers without using inductors. Moreover, gyrators will typically have higher accuracy than real inductors, due to the lower cost of precision capacitors than inductors. . The MCP6071/2/4 op amps are well suited for conditioning sensor signals in battery-powered applications. Figure 4-9 shows a two op amp instrumentation amplifier, using the MCP6072, that works well for applications requiring rejection of common mode noise at higher gains. The reference voltage (VREF) is supplied by a low impedance source. In single supply applications, VREF is typically VDD/2. RG VREF R1 R2 R2 R1 VOUT V2 1/2 MCP6072 V1 1/2 MCP6072 RL ZIN MCP6071 C R Z IN = R L + jL L = RL RC ZIN RL Equivalent Circuit L VOUT R1 2R 1 VOUT = ( V1 - V 2 ) 1 + ----- + -------- + VREF R2 RG Gyrator FIGURE 4-9: Two Op Amp Instrumentation Amplifier. To obtain the best CMRR possible, and not limit the performance by the resistor tolerances, set a high gain with the RG resistor. 4.7.3 PRECISION COMPARATOR Use high gain before a comparator to improve the latter's input offset performance. Figure 4-10 shows a gain of 11 V/V placed before a comparator. The reference voltage VREF can be any value between the supply rails. FIGURE 4-8: Gyrator. VIN MCP6071 1 M 100 k VREF MCP6541 VOUT FIGURE 4-10: Comparator. Precision, Non-inverting DS22142B-page 18 (c) 2010 Microchip Technology Inc. MCP6071/2/4 5.0 DESIGN AIDS 5.4 Microchip provides the basic design tools needed for the MCP6071/2/4 family of op amps. Analog Demonstration and Evaluation Boards 5.1 SPICE Macro Model The latest SPICE macro model for the MCP6071/2/4 op amps is available on the Microchip web site at www.microchip.com. The model was written and tested in official Orcad (Cadence) owned PSPICE. For the other simulators, it may require translation. The model covers a wide aspect of the op amp's electrical specifications. Not only does the model cover voltage, current, and resistance of the op amp, but it also covers the temperature and noise effects on the behavior of the op amp. The model has not been verified outside of the specification range listed in the op amp data sheet. The model behaviors under these conditions can not be guaranteed that it will match the actual op amp performance. Moreover, the model is intended to be an initial design tool. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to help you achieve faster time to market. For a complete listing of these boards and their corresponding user's guides and technical information, visit the Microchip web site at www.microchip.com/ analogtools. Some boards that are especially useful are: MCP6XXX Amplifier Evaluation Board 1 MCP6XXX Amplifier Evaluation Board 2 MCP6XXX Amplifier Evaluation Board 3 MCP6XXX Amplifier Evaluation Board 4 Active Filter Demo Board Kit 5/6-Pin SOT-23 Evaluation Board, P/N VSUPEV2 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board, P/N SOIC8EV * 14-Pin SOIC/TSSOP/DIP Evaluation Board, P/N SOIC14EV * * * * * * * 5.5 Application Notes 5.2 FilterLab(R) Software The following Microchip Analog Design Note and Application Notes are available on the Microchip web site at www.microchip. com/appnotes and are recommended as supplemental reference resources. * ADN003: "Select the Right Operational Amplifier for your Filtering Circuits", DS21821 * AN722: "Operational Amplifier Topologies and DC Specifications", DS00722 * AN723: "Operational Amplifier AC Specifications and Applications", DS00723 * AN884: "Driving Capacitive Loads With Op Amps", DS00884 * AN990: "Analog Sensor Conditioning Circuits - An Overview", DS00990 * AN1177: "Op Amp Precision Design: DC Errors", DS01177 * AN1228: "Op Amp Precision Design: Random Noise", DS01228 * AN1332: "Current Sensing Circuit Concepts and Fundamentals", DS01332 These application notes and others are listed in the design guide: * "Signal Chain Design Guide", DS21825 Microchip's FilterLab(R) software is an innovative software tool that simplifies analog active filter (using op amps) design. Available at no cost from the Microchip web site at www.microchip.com/filterlab, the FilterLab design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance. 5.3 MAPS (Microchip Advanced Part Selector) MAPS is a software tool that helps semiconductor professionals efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip website at www.microchip.com/ maps, the MAPS is an overall selection tool for Microchip's product portfolio that includes Analog, Memory, MCUs and DSCs. Using this tool you can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. Helpful links are also provided for Data Sheets, purchase, and sampling of Microchip parts. (c) 2010 Microchip Technology Inc. DS22142B-page 19 MCP6071/2/4 NOTES: DS22142B-page 20 (c) 2010 Microchip Technology Inc. MCP6071/2/4 6.0 6.1 PACKAGING INFORMATION Package Marking Information 5-Lead SOT-23 (MCP6071) Example: XXNN YH25 8-Lead SOIC (150 mil) (MCP6071, MCP6072) XXXXXXXX XXXXYYWW NNN Example: MCP6071E e SN^^3 1044 256 8-Lead 2x3 TDFN (MCP6071, MCP6072) XXX YWW NN Example: AHE 044 25 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2010 Microchip Technology Inc. DS22142B-page 21 MCP6071/2/4 Package Marking Information (Continuation) 14-Lead SOIC (150 mil) (MCP6074) Example: XXXXXXXXXXX XXXXXXXXXXX YYWWNNN MCP6074 E/SL e3 1044256 14-Lead TSSOP (MCP6074) Example: XXXXXXXX YYWW NNN MCP6074E 1044 256 DS22142B-page 22 (c) 2010 Microchip Technology Inc. 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DS22142B-page 23 MCP6071/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22142B-page 24 (c) 2010 Microchip Technology Inc. MCP6071/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging (c) 2010 Microchip Technology Inc. DS22142B-page 25 MCP6071/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22142B-page 26 (c) 2010 Microchip Technology Inc. MCP6071/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging (c) 2010 Microchip Technology Inc. DS22142B-page 27 MCP6071/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22142B-page 28 (c) 2010 Microchip Technology Inc. MCP6071/2/4 /HDG 3ODVWLF 'XDO )ODW 1R /HDG 3DFNDJH 01 [[ PP %RG\ >7')1@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ (c) 2010 Microchip Technology Inc. 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MCP6071/2/4 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ (c) 2010 Microchip Technology Inc. DS22142B-page 31 MCP6071/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22142B-page 32 (c) 2010 Microchip Technology Inc. MCP6071/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging (c) 2010 Microchip Technology Inc. DS22142B-page 33 MCP6071/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22142B-page 34 (c) 2010 Microchip Technology Inc. MCP6071/2/4 APPENDIX A: REVISION HISTORY Revision B (December 2010) The following is the list of modifications: 1. 2. Added new SOT-23-5 package type for MCP6071 device. Corrected Figures 2-13, 2-22, 2-23, 2-24, 2-28, 2-29 and 2-34 in Section 2.0 "Typical Performance Curves". Modified Table 3-1 to show the pin column for MCP6071, SOT-23-5 package. Updated Section 4.1.2 "Input Voltage Limits". Added Section 4.1.3 "Input Current Limits". Added new document item in Section 5.5 "Application Notes". Updated the Product Identification System page. 3. 4. 5. 6. 7. Revision A (March 2009) * Original Release of this Document. (c) 2010 Microchip Technology Inc. DS22142B-page 35 MCP6071/2/4 NOTES: DS22142B-page 36 (c) 2010 Microchip Technology Inc. MCP6071/2/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device -X Temperature Range /XX Package Examples: a) b) c) Single Op Amp Single Op Amp (Tape and Reel) (SOIC, SOT-23 and 2x3 TDFN) Dual Op Amp Dual Op Amp (Tape and Reel) (SOIC and 2x3 TDFN) Quad Op Amp Quad Op Amp (Tape and Reel) (SOIC and TSSOP) Device: MCP6071: MCP6071T: MCP6072: MCP6072T: MCP6074: MCP6074T: d) Tape and Reel, 5LD SOT-23 pkg MCP6071-E/SN: 8LD SOIC pkg MCP6071T-E/SN: Tape and Reel, 8LD SOIC pkg MCP6071T-E/MNY: Tape and Reel, 8LD 2x3 TDFN pkg MCP6072-E/SN: MCP6072T-E/SN: 8LD SOIC pkg Tape and Reel, 8LD SOIC pkg MCP6072T-E/MNY: Tape and Reel 8LD 2x3 TDFN pkg 14LD SOIC pkg Tape and Reel, 14LD SOIC pkg 14LD TSSOP pkg Tape and Reel, 14LD TSSOP pkg MCP6071T-E/OT: a) b) c) Temperature Range: E = -40C to +125C Package: MNY * OT = SL = SN = ST = = Plastic Dual Flat, No Lead, (2x3 TDFN ) 8-leadd Plastic Small Outline Transistor (SOT-23), 5-lead Plastic SOIC (150 mil Body), 14-lead Plastic SOIC, (150 mil Body), 8-lead Plastic TSSOP (4.4mm Body), 14-lead a) b) c) d) MCP6074-E/SL: MCP6074T-E/SL: MCP6074-E/ST: MCP6074T-E/ST: * Y = Nickel palladium gold manufacturing designator. Only available on the TDFN package. (c) 2010 Microchip Technology Inc. DS22142B-page 37 MCP6071/2/4 NOTES: DS22142B-page 38 (c) 2010 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-732-3 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2010 Microchip Technology Inc. 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